1. Field of the Invention
The disclosure generally relates to power management, and more specifically to methods and apparatus to avoid surges in DI/DT (rate of change of current) by throttling graphics processing unit (GPU) execution performance.
2. Description of the Related Art
Typically, power supplies for computing devices are switched-mode power supplies (SMPS) that convert a main supply alternating current (AC) power to a direct current (DC) power at one or more voltages using a high frequency switching mechanism. The voltage output of the SMPS may then be regulated by altering the duty cycle of the signal that controls the switching mechanism. The SMPS power supplies typically operate at a frequency between 50 kHz and 1 MHz. A feedback circuit is implemented to control the selected duty cycle used to generate the regulated output voltage, but the feedback circuit cannot compensate for load changes instantaneously. Consequently, varying the load (i.e., current draw) at the output of the power supply will cause a corresponding change in the output voltage before the power supply “reacts” and changes the duty cycle of the control signal.
The power requirements of the computing device attached to the power supply change dynamically based on the operations being performed as well as other factors (such as special power saving configurations of the various processing units). The more operations being performed, the larger the current draw on the power supply. A large surge in current draw causes a corresponding drop in voltage at the output of the power supply (which is then corrected by adjusting the duty cycle of the control signal for the switching mechanism). Conversely, a large drop in current draw will cause a corresponding spike in voltage at the output of the power supply. These changes in voltage supplied to the computing device may have adverse effects on the various components within the computing device. For example, the circuits of a processing unit may include various transistors or memory units (e.g., static RAM or Flip-Flops) that require a threshold voltage in order to operate reliably. When a large surge in current draw causes a corresponding drop in the supply voltage supplied to the circuit, the operation of the components may become unreliable, thereby producing random results. Conversely, a large drop in current draw corresponding to a voltage spike may cause physical harm to certain components.
Conventionally, decoupling capacitors located proximate to the various components of the computing device may provide local storage for a small amount of power that may react to fast changes in current draw instead of relying on the power supply circuit to adjust the duty cycle of the switching mechanism. However, such techniques have some drawbacks. First, adding capacitors to the computing device increases the cost and complexity of the system. These costs and complexities are exacerbated in highly parallel processors, such as graphics processing units, because such processors may have hundreds or thousands of hardware subunits that each requires separate local capacitance. Second, physical limitations of the chip design may limit the practical amount of capacitance that may be added to a circuit. Capacitors require physical space on a chip and, therefore, increasing the number of capacitors in a design may increase the size of the overall integrated circuit package. The increased size of the IC package results in a lower yield per silicon wafer and a corresponding increase in cost per chip. Finally, adding capacitance to a circuit may change the electrical characteristics of the circuit, thereby requiring longer set-up and hold times for reliable operation of the circuit components. These electrical characteristics may adversely limit the processing capacity of the processor by limiting the clock speed at which the processor may be run.
Accordingly, what is needed in the art is a system and method for throttling computing device performance to reduce large surges in current draw.